This invention relates in general to digital computer systems and in particular to the conversion of digital data between parallel and serial forms.
Digital data are represented by binary bits. Microprocessors typically operate on a number of bits of data in parallel. For example, a microprocessor chip may have 8 data lines connected to it so that 8 binary bits of digital information may be received or transmitted in parallel at any one time.
For communication between a microprocessor and a peripheral device, it is often expedient for digital data to be carried in a single line connecting them. In order to do this, the parallel data from the microprocessor must be converted to a serial bit stream for transmission over a cable.
In the example above of a microprocessor chip with 8 data lines, the 8 binary bits received or transmitted simultaneously form a character, so that the parallel data received or transmitted are in the form of a serial stream of 8 parallel bit characters. While it is convenient to manipulate data only in the form of characters all of which are of the same length, such approach is wasteful of the bandwidth of transmission channels. Thus, if a message to be transmitted is 17 bits long and each character transmitted has to be 8 bits in length, three characters will be required for conveying the message if a fixed character length protocol is used. In that case, 7 s of transimission capacity will be wasted. It is therefore desirable to adopt an approach where the characters transmitted can be of arbitrary character length. If the characters transmitted are of more than two different lengths, the microprocessor will have to keep track of the two or more different lengths of the characters, which will be cumbersome. For this reason, in conventional serializers, usually all of the characters in a message will have the same length except for the last character.
FIG. 1 illustrates a typical conventional message format using an arbitrary character length protocol. The message is made up of an opening flag 10 followed by the main body of the message itself comprising one or more normal characters 15 and one last character 19, and then concluded with a closing flag 20. The opening and closing flags are inserted in the transmitter portion of the serializer to indicate to the receiver portion of another serializer the beginning and end of the message. Typically the normal characters 15 are of fixed length (usually 8 bits or a byte). For messages of arbitrary bit length, the usual protocol is to divide it into multiples of fixed length normal characters 15 plus one final character 19 of some smaller length.
FIG. 2 illustrates the transmitter portion of a typical serializer for converting parallel data into serial data. Bit parallel, byte serial data 30 enter into the serializer through bus interface 32 and get written into FIFO (FIRST IN-FIRST-OUT) 34, and in turn go through a multiplexer 36 to be loaded successively into a shift register 38, whereby the parallel bits are shifted out as serial data 40. Since the serial data rate is in general slower than the parallel data rate, FIFO 34 is used as a storage buffer and staging area to hold the fast incoming parallel data before they have a chance of being converted into serial form. 10 The opening and closing flags of the message (see FIG. 1) are not present as they enter the serializer (see FIG. 2). These two flags are inserted into respectively the beginning and end of the serial stream by means of a special character generator 46 in conjunction with a multiplexer 36 as the message emerges from the FIFO.
Typically the normal characters are of length eight bits and, each time a character is loaded from the FIFO 34 into shift register 38, it must be shifted eight times before the next character is loaded. The number of shifts or the timing of loading the next character is controlled by a counter 42 which counts the character length corresponding to the character being shifted. Typically, the character length is initially written into a register such as register 44 by the CPU (Central processor unit) prior to the transfer of parallel data into the serializer. This character length is then loaded into counter 42 under CPU direction. In the case of a message with all its characters having the same fixed length, all its characters are thus normal characters. The CPU will first write the single character length into character length register 44 and initiate the loading of it into counter 42 at the beginning of the message transfer. Then the CPU will successively write all the rest of the characters in the message into FIFO 34. After this no further CPU action is required while the characters trickle out of the FIFO to be serialized.
In the case of a message of arbitrary bit length, conventional implementation normally requires CPU intervention to handle the odd length last character when it emerges from the FIFO to be loaded into the shift register. FIGS. 3(A), 3(B), 3(C) illustrate the critical timing problem when a message of arbitrary bit length is processed by the conventional serializer of FIG. 2. FIG. 3(A) illustrates the order in which the CPU writes or instructs. FIG. 3(B) illustrates the messsage 40 in serial bit form as it emerges from the shifter 38 and FIG. 3(C) illstrates the time window within which the CPU must complete its intervention to change the character length value in register 44.
Referring to FIGS. 3(A) and 3(B) in conjunction with FIG. 2, the CPU initially, as before, writes the character length of the normal character into the serializer before writing the normal characters into the FIFO. Since the character length stored in register 44 controls the shifting of shifter 38 by setting the value of counter 42, the value stored in register 44 cannot be changed until such value has set the counter 42 for shifting the next to last character. In other words the CPU must wait until all normal characters have come out of the FIFO before it is called upon again to reset the character length in counter 42 to that of the last character. This must be completed by the time counter 42 is called upon to control the shifter 38 to shift the correct number of times to convert the last character. The time window for setting the last character length is critical, as illustrated by FIG. 3(C), since only the time for the transmission of the next-to-last character is available. Such time-critical intervention by the CPU is undesirable since it may interfere with other CPU tasks and requires the CPU to track the retrieving of characters from the FIFO. If the CPU is not available to intervene, the retrieval of data from the FIFO may have to stop, which slows down the process. The FIFO is employed to free the CPU from having to track data flow to and retrieval from the FIFO. Requiring CPU intervention at the end of the transmitted message does not take full advantage of the time buffering function of the FIFO.
Accordingly, it is a primary object of the invention to provide a method and device which allows the transmission of messages of arbitrary bit length without requiring the normal CPU intervention at the end of the message.